module WriteBack(ALUdata_M, D_Mem_M, MemtoReg_M, Rd_M, Rd_W, RegWrite_W, RegWrite_M, writedata);

  input[15:0] ALUdata_M;
  input[15:0] D_Mem_M;
  input       RegWrite_M;

  input MemtoReg_M;
  input[2:0] Rd_M;

  output[2:0] Rd_W;
  output RegWrite_W;
 
  assign RegWrite_W = RegWrite_M;
  assign Rd_W = Rd_M;
  assign writedata = (MemtoReg_M)? D_Mem_M : ALUdata_M;

  endmodule
  
  
